Please check the lab marks we have recorded for you using the graph icon at the bottom of the course website menu, or the Give command 3222|9222 classrun -sturec from the Unix prompt in your CSE home account.
The total lab score is recorded as a mark out of 24, shown as the field "Labs".
Please let me know of any discrepancies. Thanks.
Please ensure you have your work marked off by the end of Thursday 25 October. Marks will be entered into SMS on 26 October for you to check - please await further email in this regard.
Please also complete the myExperience course survey . In particular, in the written comments, please let me know why you did/didn't attend lectures if you usually did/didn't do so .
Next week is the final week of lectures for COMP3222/9222 :(
I have a few slides to wrap up the course and preview the final exam arrangements, which I propose going over on Thursday at 1pm in the usual place. Please come along if you can make it.
I have been asked to use Tuesday to present another design example from go to whoa. For those of you who are interested and able to make it, we shall meet at 10am next Tuesday to work through the following problem, which is adapted from Katz, P7.29:
You are to develop a state diagram and VHDL description for a washing machine controller. The machine starts when a coin is deposited. It then sequences through the following stages: soak, wash, rinse and spin. There is a “double wash” switch, which, if turned on, causes a second wash and rinse to occur after the first wash and rinse have been completed. There is one timer – you may assume that each stage should take the same amount of time. The timer begins ticking as soon as the coin is deposited, generates a T signal at the end of the time period, and then resets itself and starts again. You are not required to design the timer – it is external to your controller. If the lid is raised during the spin cycle, the machine stops spinning until the lid is closed. You may assume that the timer suspends ticking while the lid is raised. Identify your inputs and outputs and draw a state diagram that implements this finite state machine. Include an asynchronous reset that forces the machine back into the initial state. Describe the finite state machine using behavioural VHDL.
Contrary to some reports, labs are on during Week 8 - the plan is to continue with Lab 7. You should complete Parts 1-4 by Week 9.
The solutions to the Quiz questions will be reviewed during Thursday's lecture this week.
Students who wish to examine their marked script may do so from 2-2:30 on Thursday in the K17 level 3 meeting room K17-302.
Thursday's quiz has been marked. You can retrieve your scores and check your lab marks to date by entering 3222 classrun -sturec if you are an undergrad, or 9222 classrun -sturec if you're a postgrad, at the UNIX prompt of your CSE home account. Alternatively, simply click on the bar chart icon at the end of the menu on the course website
The results are distributed as follows:
It's disappointing to have 46% of the class fail this early quiz. Disturbingly, this figure compares with 38% who failed it last year, and 12% two years ago.
Please note the mid-session quiz is coming up on Thursday. Please be at Ainsworth-G02 promptly by 1pm to commence the quiz and complete on time.
Welcome to Digital Circuits & Systems for Session 2, 2018!
The course outline is now available here .
Lectures start next week Tuesday morning at 9am in Ainsworth G02. Labs & tutes will start in Week 2. So...see you soon!