If you did not return your lab kit at the end of today's Practical exam, please return it as soon as possible to the CSE School Office on level 3 of building K17.
Please ensure you include your name and zID on a slip of paper inside the box so that it can be marked off a having been returned.
Unfortunately, if your lab kit is not returned, a financial block will be placed on your record. Until the block is cleared, this will prevent you from enrolling in further courses and from obtaining academic transcripts.
Thanks and have a good break!
As announced previously, the final exams are commencing at 2 pm tomorrow in the oboe, brass, sitar and kora labs on level 3 of J17. Please arrive by 1:50 pm and come prepared with writing implements and your seat allocation (see https://cgi.cse.unsw.edu.au/~exam/23T3/seating/register.cgi/allocations/ ).
The practical exam will require you to use the Quartus tools provided by the fpga-tools virtual machine available from your CSE account in the above labs. Instructions for using the tools in this way are provided on the webpage above the Quartus II Introduction PDF file at Introduction to Quartus II v13.0 . If you have never done so, practice logging onto your CSE account, starting the fpga-tools vm, unarchiving, archiving and synthesising VHDL projects as well saving files to your CSE home or USB device from the vm TODAY to avoid dismay!
Please bring a face mask to help protect you and to help prevent the spread of COVID as well as other respiratory ailments. Obviously, if you are unwell, please do not attend the exam - submit a request for special consideration instead.
Good luck with your exams!
Most lab11 submissions have been marked and uploaded, thereby completing the final Labs score for the course.
If we have not finalised your mark it is likely because we are still marking late submissions. Please get in touch with me by email if you have any query about your recorded marks, whether for labs or quizzes.