Digital Circuits and Systems COMP3222/COMP9222 26T1

Use of Vivado schematic tool to produce "paper design" in labs not permitted

Posted by Oliver Diessel Tuesday 07 April 2026, 08:43:37 AM.

The lab exercises require students to develop their design on paper and to submit their paper work as documentation accompanying their submission. We have found at least one instance of a student using the Vivado schematic tool after having coded their design to produce the desired block/circuit diagrams. This practice will not be accepted as "developing a paper design" since it is not in keeping with the intent of such exercises.

FPGA internships at Arista Networks

Posted by Oliver Diessel Thursday 02 April 2026, 03:42:03 PM.

I have received details of the following opportunity from Jenny King, an FPGA design engineer at Arista in Sydney, and a former UNSW student (graduated 2023).

"Last year we had fantastic success hiring talented interns from UNSW from your computer engineering courses. We have recently opened internship applications for 2026/27 and are hoping to share Arista's FPGA internship opportunities in a similar way this year.

I understand it is late in the term, though we would greatly appreciate if you could share this opportunity with your COMP3222 and COMP9222 students. A flyer with more details is attached. "

Quiz results available

Posted by Oliver Diessel Thursday 02 April 2026, 10:47:39 AM.

The Quiz has been marked and you should be able to see your result using the Grades (bar chart) widget at bottom left of WebCMS3 course menu.

The distribution of marks is as illustrated below. I will review some of the trickier questions during next Friday's Q&A.

Students who wish to inspect their paper may do so in K17-302 from 2 - 3 pm next Tuesday, 7 April, after the lecture. Bring your student card.

Late lab02 and on time lab03 submissions marked

Posted by Oliver Diessel Tuesday 31 March 2026, 10:20:27 AM.

The above submissions have been marked and are available for collection.