Released 23/5/22
Revised 14/6/22 to indicate lab staff available during Week 6
| Course Code | COMP4601 |
| Course Title | Design Project B |
| Units of Credit | 6 |
| Course Website | http://cse.unsw.edu.au/~cs4601 |
| Handbook Entry | http://www.handbook.unsw.edu.au/undergraduate/courses/current/COMP4601.html |
COMP4601 is a team-based project development course involving the analysis, design and implementation of embedded and/or high performance and/or low power systems using FPGAs. In 2021 we shifted the focus from VHDL implementation towards design exploration using high-level synthesis.
Teams develop a solution to one of a number of suggested project problems. Project teams are expected to investigate possible approaches, develop their proposal, present their solutions, and to report on their findings.
The course involves lectures, lab exercises, project work and seminars. Lectures will provide some context for the problems being studied and some background on solution approaches. Project teams will present the results of their investigations and developments. Students will prepare and assess seminars on advanced topics and related research publications.
The 22T2 offering of COMP4601 will be delivered online.
During the first 5 weeks, the course covers a fair amount of content at a rapid pace. Keeping up with the readings prior to each week's lectures, attending the lectures to clarify your understanding and attending the labs to actively engage in skills development are essential to picking up the material. During the second half of the course, you are expected to present and to participate in the critical assessment of seminars as well as to contribute to the development of solutions to your project problem. Project groups are free to meet when they wish. Meeting during one of the scheduled biweekly online lab sessions is recommended. Please consider your responsibilities to your colleagues and to yourself in committing to this course.
| Weeks 1-5, 7-10 online lecture/seminars | Wed 11am - 2pm |
| Weeks 1-10 online lab/project session | Wed 3pm - 5pm |
| Weeks 1-10 online lab/project session | Thu 3pm - 5pm |
Apart from teaching the elements of how to design hardware using high-level synthesis, this course is expected to enhance research skills, sharpen design, implementation and presentation skills, allow students to explore solutions to open-ended problems, and provide opportunities to practice the rapid acquisition of new technical skills with state-of-the-art technology.
By the end of this course, students should be able to:
This course contributes to the development of the following graduate capabilities:
| Graduate Capability | Acquired in |
| scholarship: understanding of their discipline in its interdisciplinary context | Design & implementation tasks; Seminars |
| scholarship: capable of independent and collaborative enquiry | Design & implementation tasks; Team activities |
| scholarship: rigorous in their analysis, critique, and reflection | Design & implementation tasks; Presentation & documentation tasks; Lab exercises |
| scholarship: able to apply their knowledge and skills to solving problems | Design & implementation tasks |
| scholarship: capable of effective communication | Presentation & documentation tasks; Seminars |
| leadership: enterprising, innovative and creative | Design & implementation tasks; Team activities |
| leadership: collaborative team workers | Team activities |
| professionalism: capable of independent, self-directed practice | Lab exercises; Design & implementation tasks |
| professionalism: capable of lifelong learning | Seminars |
| global citizens: culturally aware and capable of respecting diversity and acting in socially just/responsible ways | Team activities |
The formal pre-requisites for this course are COMP3211 and COMP3601.
It is assumed that, prior to taking this course, students:
Hardware design and systems prototyping using field-programmable gate arrays is increasingly important and supports a booming embedded systems and hardware accelerator industry. In order to develop essential skills and to be industrially relevant, computer engineering students need to gain experience designing and prototyping systems and components using programmable logic devices. Increasingly, these devices include hard processors, and therefore require designers to consider the appropriate mix of hardware and software approaches. In recent years much attention has also been given to developing high-level synthesis tools that can enhance the productivity of designers prototyping hardware solutions to computational problems. We therefore endeavour to introduce our students to this important approach to hardware design. The background necessary to understand the design problem, processors and programmable logic technology will be outlined in classes. Students will work in teams to study and develop solutions using current methodologies to a computationally demanding and relevant problem.
Formally, the course comprises three lecture hours and two lab
hours per week for 10 weeks. However, since this is a 4th year project course, there is an emphasis on working informally with your peers to solve problems. It is expected that you will spend a good deal of time both independently and jointly solving problems you encounter and trying to understand vaguely stated, but important information. On average, you can expect to need to spend 15 hours per week on this course.
Course participants will study motivating problems during class and undertake practical tasks to gain an appreciation of the main concepts touched upon in the course, namely: high-level synthesis, hardware acceleration, hardware/software co-design, parallel architectures and reconfigurable systems design.The problems to be studied and possible solution approaches will be introduced via lectures. You are expected to prepare for each lecture by reading the relevant chapter before the lecture.
Please read Chapter 1 of the text, Parallel Programming for FPGAs , before the lecture in Week 1.
In 21T2, a new set of laboratory exercises was developed to facilitate the acquisition of the skills required to make use of the hardware/software provided in the course. These have been revised in 22T2 to provide greater clarity. Students will work through these exercises and hand in their findings on selected questions each week.
In this course you will partner with fellow students in two types of groups: project and seminar groups. Your project group will decide which problem to study and will jointly work towards an efficient implementation. Your seminar group will study a relevant topic or theme via a set of suggested papers and prepare a joint presentation. The project and seminar tasks both comprise individual and team evaluation components. Overall, your individual efforts will contribute 60% to your final mark in the course.
Project teams are required to report on their progress as they develop solutions to the unique design challenges posed by their projects. A project plan is to be developed and presented to the demonstrators at any time (when teams are ready) but during the scheduled lab sessions in Week 5 at the latest. A final report, demonstration and presentation are due when teams are ready, but during the scheduled lab sessions in Week 10 at the latest. These formal reporting requirements encourage students to manage their project systematically and to plan their work. Feedback on the direction and approach being taken will be provided during the lab sessions in Weeks 5 - 10.
The preparation and presentation of seminars is intended to provide students with research experience, practice effective communications, and develop professional skills. Audience members are expected to participate in the discussion and to assess the presentation of seminars.
Due to the nature of team projects and group seminars, all members of a team/group need to actively participate and contribute to achieve common goals. Please let the course staff know if you would like to discuss your team's effectiveness - while we can't promise miracle solutions, we'll try to help maximise your team's potential.
There are no formal examinations in this course.
Assessment in this course will be based on the following:
| Criterion | Week due | Contribution |
| Lab component | 40% | |
| Lab hand ins | Mondays, Weeks 3, 4, 6 & 8 | 40% i(ndividual) |
| Seminar component | 20% | |
| Seminar presentations | Wednesday lectures, Weeks 7-10 | 10% T(eam) |
| Seminar participation & assessment | Wednesday lectures, Weeks 7-10 | 10% i(individual) |
| Project component | 40% | |
| Individual project contribution |
|
10% i(individual) |
| Project plan (presentation & report) | Lab sessions, Week 5 | 10% T(eam) |
| Final project presentation, demonstration & report | Lab sessions, Week 10 | 20% T |
Individual assessments - worth 60% of your assessment in total - will be based on individual efforts, individual contributions to team successes, your learning, and ability to adapt to circumstances.
UNSW has an ongoing commitment to fostering a culture of learning informed by academic integrity. All UNSW staff and students have a responsibility to adhere to this principle of academic integrity. Plagiarism undermines academic integrity and is not tolerated at UNSW. Plagiarism at UNSW is defined as using the words or ideas of others and presenting them as your own.
If you haven't done so yet, please take the time to read the full text of
The pages below describe the policies and procedures in more detail:
This section explains the weekly schedule of activities, organisational deadlines and due dates for the course.
| Week | Weekday | Time | Activity |
| 1 - 5 | Wednesdays | 11:00 - 14:00 | Online lecture |
| Wednesdays | 15:00 - 17:00 | Online lab session | |
| Thursdays | 15:00 - 17:00 | Online lab session | |
| 6 |
No scheduled activities;
Lab demonstrators available online at usual times |
||
| 7 - 10 | Wednesdays | 11:00 - 14:00 | Online seminars |
| Wednesdays | 15:00 - 17:00 | Online lab session/project support | |
| Thursdays | 15:00 - 17:00 | Online lab session/project support |
| Week | Deadline |
| 2 | Project teams organised |
| 3 |
Project teams finalised
Seminar topics chosen |
| 4 | Finalise seminar groups |
| 5 | Complete project plans |
| 10 | Present project outcomes |
| Week | Weekday | Time | Deliverable |
| 3, 4, 6 & 8 | Mondays | 17:00 | Lab hand-ins for Week 2, 3, 4 & 7 exercises |
| 5 | Wednesday | 15:00 - 17:00 | Project plan presentation & report |
| Thursday | 15:00 - 17:00 | Project plan presentation & report | |
| 7 - 10 | Wednesdays | 11:00 - 14:00 | Seminar presentations & assessments |
| 10 | Wednesdays | 15:00 - 17:00 | Final project demos, presentations & reports |
| Thursdays | 15:00 - 17:00 | Final project demos, presentations & reports |
During the first 5 weeks of lectures, we will be discussing the content of the online book Parallel Programming for FPGAs by Ryan Kastner, Janarbek Matai and Stephen Neuendorfer . Lab exercises will be also be based on exercises suggested in this text. We will use the 2020.1 version of Vivado and Vitis tools from Xilinx and target the Xilinx Zynq 7020 device hosted on ZedBoards. Students will be guided in their uptake of the tools via Xilinx tutorials and guides prepared by the teaching staff.
Students will need to refer to research papers, product data sheets, application notes, standards, system documentation, reference books and technical articles to gain the background needed to design and implement the project systems. Some of these references will be identified during the course. Please ask the lecturer and/or demonstrators for assistance if you are lost.
Student feedback on this course will be obtained via electronic survey (myExperience) at the end of session and will be used to make improvements to the course. Students are encouraged to provide informal feedback during the session and to let the lecturer in charge know of any problems as soon as they arise . Every reasonable effort to address concerns will be made.
In 2021, the course was updated to focus on high-level synthesis in FPGA design. The 2021 myExperience feedback was overwhelmingly positive - students appear to have appreciated the change of emphasis and come away thinking they had learned a few things. A number of comments were received that suggested I should have released the projects earlier and provided more time to complete the projects; a couple of comments indicated the seminar topics were too broad; and a couple commented that there was too much work and that marking rubrics were not clear enough. Hmmm. In 22T2 I have moved the projects forwards with plans to be presented in Week 5. To accommodate this shift, I have provided some breathing space by delaying the deadlines for the latter two lab hand-ins. I will also include a few more seminars that are more directly related to high-level synthesis and remove topics that might be considered too esoteric for serious young engineers. Yes, there is a lot to do in the course, but this is a final core course. I'm primarily focussed on a decent learning experience not something too shallow or too soul-destroying. And I agree that it is desirable to have a prescription for how every mark is earned spelled out in advance, just like in real life. I promise I will try to be fair. Please let me know if there is something you think I can improve!
Resource created Friday 20 May 2022, 10:49:53 AM, last modified Tuesday 14 June 2022, 11:40:17 AM.