Released 16/5/22
| Course Code | COMP4601 |
| Course Title | Design Project B |
| Units of Credit | 6 |
| Course Website | http://cse.unsw.edu.au/~cs4601 |
| Handbook Entry | http://www.handbook.unsw.edu.au/undergraduate/courses/current/COMP4601.html |
COMP4601 is a team-based project development course involving the analysis, design and implementation of embedded, high performance or low power FPGA-based accelerators using high-level synthesis.
Students study concepts through lectures and guided lab exercises during the first half of the course, when project teams are also formed and the project goals are developed. During the second half of the course, students are involved in presenting group seminars and working on their projects. The course finishes with final project presentations.
The 23T2 offering of COMP4601 will be delivered in person.
During the first 5 weeks, the course covers a fair amount of content at a rapid pace. Keeping up with the readings prior to each week's lectures, attending the lectures to clarify your understanding and attending the labs to actively engage in skills development are essential to picking up the material.
During the second half of the course, you are expected to present and to participate in the critical assessment of seminars as well as to contribute to the development of solutions to your project problem. Project groups are free to meet when they wish. Meeting during one of the scheduled biweekly online lab sessions is recommended.
Please consider your responsibilities to your class mates and to yourself in committing to this course.
| Weeks 1-5, 7-10 lecture/seminars | Tue 9am - 12pm, Pat O'Shane G03 (previously CLB2) |
| Weeks 1-5, 7-10 lab/project session | Wed 2pm - 4pm, Brass Lab ME305 |
| Weeks 1-5, 7-10 additional lab/project session |
Thu 6pm - 8pm, Brass Lab ME305
|
| Week 6 online lab/project help session | Wed 2pm - 4pm, Teams |
Apart from teaching the elements of how to design hardware using high-level synthesis and gaining an understanding of accelerator design, this course enhances research skills, sharpens design, implementation and presentation skills, allow students to explore solutions to open-ended problems, and provides opportunities to practice the rapid acquisition of new technical skills with state-of-the-art technology.
By the end of this course, students should be able to:
This course contributes to the development of the following graduate capabilities:
| Graduate Capability | Acquired in |
| scholarship: understanding of their discipline in its interdisciplinary context | Design & implementation tasks; Seminars |
| scholarship: capable of independent and collaborative enquiry | Design & implementation tasks; Team activities; Seminars |
| scholarship: rigorous in their analysis, critique, and reflection | Design & implementation tasks; Presentation & documentation tasks; Lab exercises |
| scholarship: able to apply their knowledge and skills to solving problems | Design & implementation tasks |
| scholarship: capable of effective communication | Presentation & documentation tasks; Seminars |
| leadership: enterprising, innovative and creative | Design & implementation tasks; Team activities |
| leadership: collaborative team workers | Team activities |
| professionalism: capable of independent, self-directed practice | Lab exercises; Design & implementation tasks |
| professionalism: capable of lifelong learning | Seminars |
| global citizens: culturally aware and capable of respecting diversity and acting in socially just/responsible ways | Team activities |
The formal pre-requisites for this course are COMP3211 and COMP3601.
It is assumed that, prior to taking this course, students:
Hardware design and systems prototyping using field-programmable gate arrays is increasingly important and supports a booming embedded systems and hardware accelerator industry. In order to develop essential skills and to be industrially relevant, computer engineering students need to gain experience designing and prototyping systems and components using programmable logic devices. Increasingly, these devices include hard processors, and therefore require designers to consider the appropriate mix of hardware and software approaches. In recent years much attention has also been given to using high-level synthesis tools that can enhance the productivity of designers prototyping hardware solutions to computational problems. We therefore endeavour to introduce our students to this important approach to hardware design. The background necessary to understand the design problem, processors and programmable logic technology will be outlined in classes. Students will work in teams to study and develop solutions using current methodologies to a computationally demanding and relevant problem.
Formally, the course comprises three lecture hours and two lab
hours per week for 10 weeks. However, since this is a 4th year project course, there is an emphasis on working informally with your peers to solve problems. It is expected that you will spend a good deal of time both independently and jointly solving problems you encounter and trying to understand vaguely stated, but important information. On average, you can expect to need to spend 15 hours per week on this course, and perhaps more to excel.
Course participants will study motivating problems during class and undertake practical tasks to gain an appreciation of the main concepts touched upon in the course, namely: high-level synthesis, hardware acceleration, hardware/software co-design, parallel architectures and reconfigurable systems design.The problems to be studied, and possible solution approaches will be introduced via lectures. You are expected to prepare for each lecture by reading the relevant chapter before the lecture.
Please read Chapter 1 of the text, Parallel Programming for FPGAs , before the lecture in Week 1.
Laboratory exercises study certain example problems in more depth to facilitate the acquisition of the skills required to make use of the hardware/software provided in the course. Students will work through these exercises and hand in their findings on selected questions.
In this course you will partner with fellow students in two types of groups: project and seminar groups. Your project group will decide which problem to study and will jointly work towards an efficient implementation. Your seminar group will study a relevant topic or theme via a set of suggested papers and prepare a joint presentation. The project and seminar tasks both comprise individual and team evaluation components.
Project teams are required to report on their progress as they develop solutions to the unique design challenges posed by their projects. A project plan is to be developed and presented to the class during the scheduled lab sessions in Week 5. A final report, demonstration and presentation are made during the scheduled lab sessions in Week 10 at the latest. These formal reporting requirements encourage students to manage their projects. Guidance and feedback will be provided as needed/requested during lab sessions.
The preparation and presentation of seminars is intended to provide students with research experience, practice effective communications, and develop professional skills. Audience members are expected to participate in the discussion and to assess the presentation of seminars.
Due to the nature of team projects and group seminars, all members of a team/group are expected to actively participate and contribute to achieve common goals. Please let the course staff know if you would like to discuss your team's effectiveness - while we can't promise miracle solutions, we'll try to help maximise your team's potential.
There are no formal examinations in this course.
Assessment in this course will be based on the following:
| Criterion | Week due | Contribution |
| Lab component | 40% | |
| Four lab hand ins | Mondays, Weeks 3, 4, 6 & 8 | 40% i(ndividual) |
| Seminar component | 20% | |
| Seminar presentations | Tuesday lectures, Weeks 7-10 | 10% T(eam) |
| Seminar participation & assessment | Tuesday lectures, Weeks 7-10 | 10% i(individual) |
| Project component | 40% | |
| Individual project contribution |
|
10% i(individual) |
| Project plan (presentation & report) | Lab sessions, Week 5 | 10% T(eam) |
| Final project presentation, demonstration & report | Lab sessions, Week 10 | 20% T(eam) |
Individual assessments - worth 60% of your assessment in total - will be based on individual efforts, individual contributions to team successes, your learning, and ability to adapt to circumstances.
UNSW has an ongoing commitment to fostering a culture of learning informed by academic integrity. All UNSW staff and students have a responsibility to adhere to this principle of academic integrity. Plagiarism undermines academic integrity and is not tolerated at UNSW. Plagiarism at UNSW is defined as using the words or ideas of others and presenting them as your own.
If you haven't done so yet, please take the time to read the full text of
The pages below describe the policies and procedures in more detail:
This section explains the weekly schedule of activities, organisational deadlines and due dates for the course.
| Week | Weekday | Time | Activity |
| 1 - 5 | Tuesdays | 9:00 - 12:00 | In person lecture |
| Wednesdays | 14:00 - 16:00 | In person lab session | |
| Thursdays | 18:00 - 20:00 | Additional in person lab session | |
| 6 | Wednesday | 14:00 - 16:00 | Online lab/project help |
| 7 - 10 | Tuesdays | 9:00 - 12:00 | In person seminars |
| Wednesdays | 14:00 - 16:00 | In person lab session/project support | |
| Thursdays | 18:00 - 20:00 | Additional in person lab session/project support |
| Week | Deadline |
| 2 | Project teams organised; email topic, membership, spokesperson details to Oliver |
| 3 |
Project teams finalised
Seminar topics chosen |
| 4 | Finalise seminar groups |
| 5 | Complete project plans; email PDF to Oliver |
| 10 | Present project outcomes; email PDF to Oliver |
| Week | Weekday | Time | Deliverable |
| 3, 4, 6 & 8 | Mondays | 17:00 | Lab hand-ins for Week 2, 3, 4 & 7 exercises |
| 5 | Wednesday | 14:00 - 16:00 | Project plan presentations |
| Thursday | 18:00 - 20:00 | Remaining project plan presentations | |
| Friday | 17:00 | Email PDF of plan to Oliver | |
| 7 - 10 | Tuesdays | 9:00 - 12:00 | Seminar presentations & assessments |
| 10 | Wednesday | 14:00 - 16:00 | Final project demos & presentations |
| Thursday | 18:00 - 20:00 | Final project demos & presentations | |
| Friday | 17:00 | Email PDF of final report to Oliver |
During the first 5 weeks of lectures, we will be discussing the content of the electronic book Parallel Programming for FPGAs by Ryan Kastner, Janarbek Matai and Stephen Neuendorfer . Lab exercises will be also be based on exercises suggested in this text. We will use the 2020.1 version of Vivado HLS and 2021.2 Vitis tools from Xilinx and target the KV260 Kria boards. For students who would like to use a ZedBoard, these are also available. Students will be guided in their uptake of the tools via Xilinx tutorials and guides prepared by the teaching staff.
Students will need to refer to research papers, product data sheets, application notes, standards, system documentation, reference books and technical articles to gain the background needed to design and implement the project systems. Some of these references will be identified during the course. Please ask the lecturer and/or demonstrators for assistance if you are lost.
Student feedback on this course will be obtained via electronic survey (myExperience) at the end of session and will be used to make improvements to the course. Students are encouraged to provide informal feedback during the session and to let the lecturer in charge know of any problems as soon as they arise . Every reasonable effort to address concerns will be made.
I've read over myExperience responses from 2022. These could be summarised on the positive side as appreciating the variety of activities and range of topics covered in this course, as well as the flexibility taken with respect to projects. Critical comments related to inadequate guidance as to the amount of work expected for lab hand-ins, the amount of work, and the intensity of the seminar section. This year I will try to provide a little more guidance on what I'm expecting, both in terms of lab hand-ins and seminar coverage. Most importantly, I want you to come away feeling you have learnt something from the course, and that you feel more confident to explore these/similar ideas further in the future. Please let me know if there is something you think I can improve!
Resource created Tuesday 16 May 2023, 10:34:24 AM, last modified Tuesday 16 May 2023, 02:32:18 PM.